Recent years have seen a beginning of widespread use of, for example, “twin panel” mobile telephones and similar displays equipped with two display panels. FIG. 25 shows an example. As in FIG. 25, a twin-panel display 181 has a main panel 182 and a sub-panel 183.
The main panel 182 includes a TFT substrate 184 which is a board carrying thin film transistors (TFTs) 192 thereon; an opposite substrate 185 placed opposite to the TFT substrate 184; and a liquid crystal layer (LC) 194 as a display medium sandwiched between the TFT substrate 184 and the opposite substrate 185.
On the TFT substrate 184 are there provided gate bus lines 188 and source bus lines 189. TFTs 192 are laid out near the intersections of the gate bus lines 188 and the source bus lines 189. The TFT 192 is connected to a gate bus line 188 at the gate, a source bus line 189 at the source, and a pixel electrode at the drain. A voltage is then applied to the LC (pixel) 194 between the pixel electrode and a common electrode (COM) 193 on the opposite substrate 185. All the TFTs 192 undergo the same process, displaying an image.
The main panel 182 further includes a gate driver 190 and a source driver 191. The lines extending from the gate driver 190 are connected to the gate bus lines 188, and those extending from the source driver 191 are connected to the source bus lines 189, so that the gate driver 190 and the source driver 191 can apply gate signal voltages and source signal voltages to respective bus lines.
The sub-panel 183 includes a TFT substrate 186 which is a board carrying thin film transistors 192 thereon; an opposite substrate 187 placed opposite to the TFT substrate 186; and a liquid crystal layer (LC) 194 as a display medium sandwiched between the TFT substrate 186 and the opposite substrate 187.
The sub-panel 183 is connected to the main panel 182 through, for example, an FPC (flexible printed circuit) not shown in the figure. The connection enables the gate driver 190 and the source driver 191 on the main panel 182 to apply gate signal voltages and source signal voltages to the bus lines on the sub-panel 183 through, for example, the wiring on the main panel 182 and the FPC.
The TFT substrate 186 is provided with gate bus lines 188 and source bus lines 189. TFT 192 are laid out near the intersections of the gate bus lines 188 and the source bus lines 189. The TFT 192 is connected to a gate bus line 188 at the gate, a source bus line 189 at the source, and a pixel electrode at the drain. A voltage is then applied to the LC (pixel) 194 between the pixel electrode and a common electrode (COM) 193 on the opposite substrate 187. All the TFTs 192 undergo the same process, displaying an image.
Thus, the main panel 182 and the sub-panel 183 can display an image. The shared bus lines to the main panel 182 and the sub-panel 183 are not limited to the source bus lines 189 in FIG. 25; they may be the gate bus lines.
As to conventional active matrix liquid crystal displays, for example, Japanese Published Unexamined Patent Application 7-168208 (Tokukaihei 7-168208/1995; published on Jul. 4, 1995) discloses an arrangement in which drive signals are fed through coupling capacitances which are made almost equal to one another. The arrangement produces a display free from irregularities.
In the twin-panel display 181, the main panel 182 suffers block split and other defects in image display due to delays of source signals on some source bus lines.
Specifically, as shown in FIG. 25, the twin panel 181 has different numbers of source bus lines 189 for the main panel 182 and the sub-panel 183. Those for the main panel 182 are divided into two groups: a first group 195 of lines that is shared with the sub-panel 183 and a second group 196 of lines that is not.
The first group 195 of lines is capacitance loaded by the sub-panel 183, as well as by the main panel 182, upon driving the main panel 182; therefore, supposing that the main panel 182 has a capacitance of 20 pF and the sub-panel has a capacitance of 10 pF, the capacitance for the first group 195 of lines is 30 pF. On the other hand, the second group 196 of lines is not capacitance loaded by the sub-panel 183; therefore, the capacitance for each one of the second group 196 of lines is 20 pF.
Upon producing a display on the main panel 182, the difference in capacitance renders differences in source signal delays distinct between the boundary between the first and second groups 195, 196, causing block split and other display defects. “Block split” is an irregular display which occurs in a certain block of a display panel, and caused by difference in delay among signals on lines arranged to form a matrix in the display panel.